Behavioral synthesis is a technology that allows circuit designers to express hardware design functionality in algorithmic terms, and then transform that functionality into a structure that permits implementation in actual hardware, such as logic circuits. Behavioral synthesis is used as part of a behavioral design flow that promises to raise the level of abstraction of the design process for modern digital circuits. Through behavioral synthesis, designer productivity can be increased and the opportunity for error can be reduced.
Starting with an algorithmic description of a digital design function in a high-level language, behavioral synthesis tools automatically create, from the algorithmic description, the cycle-by-cycle detail needed for hardware implementation. Typically, the high-level algorithmic description of a design is encoded using C or C++ or another high-level language, and is then converted by the behavioral synthesis tools into lower-level abstractions that can be used by other parts of the process. An example of a lower-level abstraction is a register transfer level (RTL) implementation, which may be embodied in a description language such as Verilog or others. Another example of a lower-level abstraction is a gate-level description comprising of an interconnected network of models for primitive logic devices.
The behavioral synthesis tools transform un-timed or partially timed functional code into fully timed models. These RTL and gate-level models are used directly in a conventional logic synthesis flow to create a gate-level implementation for the entire design function. Further details about behavioral synthesis can be found throughout existing technical and academic publications.
Improvements, however, are needed in order to optimize the behavioral design process. For example, during the behavioral design process, the C/C++ code in the algorithmic description is often interpreted sequentially or in series by the behavioral synthesis tool(s). The behavioral design process can therefore become lengthy and/or inefficient if the algorithmic description involves hundreds (if not thousands) of lines of code and many repetitive operations, each of which may need to be individually interpreted in sequence/series by the behavioral synthesis tool(s).